The present invention concerns the processing of semiconductor devices and pertains particularly to an integrated etch process for polysilicon/metal gate.
Polysilicon is often the material of choice for the gates of field effect transistors formed on an integrated circuit because of the stability of polysilicon and the compatibility of polysilicon with silicon processing technology. However, the relatively high electrical resistivity of polysilicon typically requires heavy doping and metallization in order to achieve acceptable performance. As the gate length is scaled down, gate resistance becomes an increasingly significant factor limiting the operating speed of integrated circuits.
Gate metallization technologies have become an increasingly important in meeting the challenges posed by shrinking gate dimensions. For example, self-aligned silicide techniques are used to provide metallization of transistor gates. However, as device dimensions continue to decrease, the silicide metallization dimensions also typically decrease. When the silicide gate metallization becomes too thin, an unacceptably high sheet resistance can result. This is further complicated by narrow-line width effects for some silicide processes.
An ideal solution is to use a highly conductive material for the gate, such as an elemental metal, that substantially lowers sheet resistance and generally eliminates the narrow-line width problems posed by some silicide techniques. Unfortunately, the substitution of part or all of a polysilicon gate with an elemental metal significantly complicates conventional semiconductor processing. For example, most suitable metals are unacceptably degraded by the chemicals and high temperatures encountered during the early stages of semiconductor device processing. This limitation generally precludes introduction of the metal as part of initial lithographic gate patterning. If the metal is introduced during later stages, a dedicated masking and lithography procedure to modify earlier patterned gates for the metal is typically required. With decreasing gate size, such a dedicated procedure is difficult to accurately align and execute.
Thus, there is a need for processing techniques which allow for efficient self-aligned processing of transistor gates.